Accelerating Mobile Computing Chip Development: A Case Study of Nufront and Cadence
Technology Category
- Analytics & Modeling - Digital Twin / Simulation
- Platform as a Service (PaaS) - Application Development Platforms
Applicable Industries
- Electrical Grids
- Transportation
Applicable Functions
- Product Research & Development
- Quality Assurance
Use Cases
- Virtual Prototyping & Product Testing
- Virtual Reality
Services
- System Integration
- Testing & Certification
About The Customer
Nufront is a Chinese technology company that develops systems and solutions in the areas of wireless broadband communication and broadcasting, integrated circuit (IC) design, video search, digital-image processing, intelligent transportation, and digital medical. The company expands its reach and capabilities beyond its own research and development (R&D) team by collaborating with industry-leading companies, universities, and academic institutes based in China. An innovative company, Nufront has been issued approximately 200 patents in the areas of mobile multimedia, wireless broadband, smart central processing unit (CPU) design, video search, and digital-image technology for counterfeit identification and authentication.
The Challenge
Nufront, a Chinese technology company, was tasked with the challenge of developing its third-generation mobile computing chip, the NS115, based on the ARM® Cortex™-A9 dual-core processor. The company had to adhere to strict mobile-computing platform requirements, achieve extremely low levels of power consumption, and ensure a high level of performance. The design team’s challenge was to verify and emulate the chip with a focus on performance and power with Android applications. The NS115 required a complex design with 12 million (12M) gates and had to meet Android system requirements, including the need for external storage, multiple screen displays, the ability to accept data input from various sources, and a long lead-time for IC simulation. The Nufront team felt that register-transfer level (RTL) simulation would be too slow for system-level verification, and frequent design iterations and the lack of full debug visibility wasn’t suitable to choose a field-programmable gate array (FPGA)-based solution.
The Solution
Nufront chose the Cadence® Palladium® XP Verification Computing Platform to emulate the NS115, enabling early system-level integration and software validation for Android and Linux while speeding time to delivery and enhancing overall quality. The Palladium XP platform integrates with Cadence Incisive® Enterprise Manager to support a metric-driven flow that accelerates verification. Nufront engineers were able to use a common verification plan and extract constraint results from multiple locations into a common database for metric analysis. The Nufront team relied upon Palladium XP for system-level power analysis and power verification. Palladium XP Dynamic Power Analysis enabled them to quickly identify peak and average power of their system-on-chip (SoC) with deep software cycles. During the runs, they identified and zoomed into power peaks with finer granularity to identify the high power consumers in the design. This helped them reduce overall power consumption. The Cadence solution also allows the reuse of abstracted models such as C/C++, transaction-level models, behavioral RTL, RTL/ gate-level netlist, silicon/FPGA/software IP, and system-level interfaces.
Operational Impact
Quantitative Benefit
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