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IoT in Retail: L’Occitane's Innovative Store Launch and Sampling Campaign - Cadence Design Systems Industrial IoT Case Study
IoT in Retail: L’Occitane's Innovative Store Launch and Sampling Campaign
L’Occitane, a global beauty brand known for its sensorial, natural beauty products, was faced with the challenge of raising awareness for the opening of its new flagship store on Regent Street, London. The brand wanted to not only drive traffic to the new store but also educate consumers about its unique holistic beauty offerings. The new store was designed to offer customers a unique experience, engaging all senses and providing a retreat from the busy streets of Central London. The challenge was to create a campaign that would effectively communicate the brand's positioning and the unique offerings of the new store, while also attracting a significant number of visitors.
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Sharp Corporation Accelerates CMOS Image Sensor Production with Cadence Solutions - Cadence Design Systems Industrial IoT Case Study
Sharp Corporation Accelerates CMOS Image Sensor Production with Cadence Solutions
Sharp Corporation, a global electronics company based in Japan, was faced with the challenge of speeding up the time to market for a new CMOS image sensor without compromising on product quality. The market for sensors and micro-electromechanical systems (MEMS) devices was rapidly expanding, driven by the increasing demand for user-friendly consumer electronics in various sectors including automobiles, computers, medical equipment, and portable products such as media players, tablets, and smartphones. This put immense pressure on Sharp to produce highly differentiated products within increasingly tight timeframes. The design challenge was to address timing and routability convergence challenges.
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NVIDIA and Cadence: Streamlining PCB Design with IoT - Cadence Design Systems Industrial IoT Case Study
NVIDIA and Cadence: Streamlining PCB Design with IoT
NVIDIA, a leading company in visual computing technologies, was facing a significant challenge in meeting the stringent time-to-market windows for its high-performance gadgets. The company's average design cycle was less than six months, from silicon tapeout to printed circuit boards (PCBs) ready for the marketplace. NVIDIA design teams were using Cadence tools to create their IC package and board designs. They had also developed several in-house tools for ball grid array (BGA) fanout and routing to augment their existing Cadence® Allegro® constraint-driven PCB design flow. However, the pressures of product miniaturization and high-density interconnect (HDI), combined with an increasing number of constraints, was creating new challenges. The question was whether to invest time and resources developing tools to enable HDI, or to adopt a new solution. And since NVIDIA was designing with high-speed constraints but also using “build-up” technology to handle BGA fanout, they would need a highly flexible solution that could address both sets of requirements.
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Samsung and Cadence: Accelerating SSD Product Development with IoT - Cadence Design Systems Industrial IoT Case Study
Samsung and Cadence: Accelerating SSD Product Development with IoT
Samsung, a market leader in solid-state drives (SSDs), decided to add a PCI Express interface to its SSD controllers in 2012 to increase data transfer performance and expand its market share. Traditionally, SSDs were based on the SATA protocol used for HDDs, which was compatible but had performance and throughput limitations when used with non-volatile memory. The addition of PCI Express to Samsung’s SSD significantly increased the challenges faced in device and software validation, particularly at the system-on-chip (SoC) level. This required a significant performance increase in the validation environment to validate PCI Express behavior at the SoC level, integrate and debug host driver software, and validate end-to-end bulk DMA transfers. Samsung initially attempted to use their traditional approach—a simulated testbench using simulation verification IP (VIP)—but found it too slow and inefficient for their needs with the PCI Express interface.
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Fujitsu and Cadence: Revolutionizing Mobile WiMAX with Power-Optimized Design - Cadence Design Systems Industrial IoT Case Study
Fujitsu and Cadence: Revolutionizing Mobile WiMAX with Power-Optimized Design
Fujitsu Microelectronics Limited, a global leader in microelectronics for computers and communication devices, was faced with the challenge of making mobile WiMAX a reality by reducing chip size and power requirements. The key to achieving this was optimizing the power design for the lowest possible overall usage and shutoff leakage. Previously, independent decisions made at each stage of the design process often impacted other areas in unforeseen ways, adversely affecting the final power characteristics. The challenge was further compounded by the need to align power design around CPF with accurate simulation, move to smaller geometries, reduce design time, and improve the quality of silicon.
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Freescale Semiconductor's Transition to UVM-MS for Enhanced Verification Efficiency - Cadence Design Systems Industrial IoT Case Study
Freescale Semiconductor's Transition to UVM-MS for Enhanced Verification Efficiency
Freescale Semiconductor, a leader in embedded processing solutions, faced a significant challenge in improving the efficiency of top-level verification of mixed-signal Systems on Chip (SoCs). The company's analog and sensors division, which primarily manages analog components, was grappling with the increasing use of digital logic in new projects. Most analog engineers had limited expertise in design verification languages, yet their involvement in executing top-level verification of mixed-signal SoCs was crucial. The traditional testbenches created by analog engineers were based on schematic entry and multiple configuration views, and relied on waveform inspection. However, advanced verification methodologies were typically digital-centric, command-line driven, and based on object-oriented languages such as SystemVerilog. This posed a significant challenge in bridging the gap between analog and digital verification methodologies.
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Teradyne's Productivity and Quality Improvement with Cadence's Virtuoso Multi-Mode Simulation - Cadence Design Systems Industrial IoT Case Study
Teradyne's Productivity and Quality Improvement with Cadence's Virtuoso Multi-Mode Simulation
Teradyne, a leader in providing automatic test equipment (ATE) to component manufacturers, was faced with the challenge of improving the productivity and quality of silicon. The company designs systems with advanced custom chip sets and wanted to implement a single, flexible methodology for use in its design and verification of complex mixed-signal systems on chip (SoCs), and across a wide range of other integrated circuits (ICs). Key considerations for Teradyne were simulation capacity for very complex analog mixed-signal designs and the ability to dynamically adapt to changing design priorities. The design challenges included complex analog and mixed-signal SoC simulations and a wide variety of applications and test priorities.
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Ricoh Accelerates Development Cycle for Multifunction Printer ASICs with Cadence - Cadence Design Systems Industrial IoT Case Study
Ricoh Accelerates Development Cycle for Multifunction Printer ASICs with Cadence
Ricoh, a leading provider of office equipment, was facing challenges in speeding up the development cycle for its multifunction printer ASICs to keep pace with the fast-moving market. The company identified two significant areas for improvement. Firstly, there was a lack of effective solutions to avoid missing test cases and test implementations, leading to errors in the testing process. About 22% of their errors stemmed from insufficient data extraction into the testbench and wrong test implementation due to misinterpretation of the specification. Secondly, Ricoh was spending too much time, about three hours each day, just capturing the verification status for progress management manually from a team of 26 verification engineers. This excluded time spent diagnosing actual problems. Ricoh needed to automate this data collection and filtering process, so the engineers could start resolving problems sooner.
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Pegatron Boosts Productivity with Cadence's Allegro PCB Designer - Cadence Design Systems Industrial IoT Case Study
Pegatron Boosts Productivity with Cadence's Allegro PCB Designer
Pegatron Corporation, a leading electronics manufacturing company, was facing a significant challenge in its product development process. The company's layout team was spending an excessive amount of time manually routing and tuning the traces on PCBs developed for notebook, tablet, and server products. The process was slow and labor-intensive, particularly when dealing with complex ball-grid array (BGA) packages that could have up to 1,000 pins. The company's customers were also demanding more detailed evaluations, requesting 100 percent routing, including tuning. This situation was limiting the number of projects the team could handle and was causing frustration among the team members. To increase their productivity and meet customer demands, the team needed a way to automate the routing process.
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VIA Telecom's Enhanced Productivity with Cadence Solutions - Cadence Design Systems Industrial IoT Case Study
VIA Telecom's Enhanced Productivity with Cadence Solutions
VIA Telecom, a leading fabless semiconductor company, was facing a significant challenge in delivering low-power baseband processors in a highly competitive market. The company's customers, primarily handset manufacturers, were under increasing pressure to deliver unique mobile devices with low power consumption and long battery life. These customers were also facing shortened design cycles due to time-to-market demands. To keep pace with its customers, VIA Telecom needed to move away from its manual process for verifying the power intent of its digital baseband processor designs. The company was seeking a proven solution with strong support to automate this process and maintain low power consumption while ensuring timely delivery of their products.
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IBM and Cadence: Streamlining Mainframe Computer Designs with Complex PCB Systems - Cadence Design Systems Industrial IoT Case Study
IBM and Cadence: Streamlining Mainframe Computer Designs with Complex PCB Systems
IBM, a leader in mainframe computing, was facing challenges in designing highly complex printed circuit boards (PCBs) for their mainframe computers. These PCBs, measuring as large as 50cm x 60cm, carry tens of thousands of signal interconnects in more than 10 layers of circuitry, with pin counts reaching 5,000 per component and more than 5,000 connections at the board level. The complexity of these designs made traditional schematics cumbersome and time-consuming to work with and analyze. IBM attempted to simplify the process by developing a solution based on entering the design attributes of each signal in a table or spreadsheet format. However, this added another step in the process as engineers had to convert the information into Hardware Description Language (HDL) to interface with the design platform. Additionally, analog elements could not be treated in this way and had to be configured manually.
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Accelerating Timing Closure on High-Speed Interfaces with Allegro TimingVision Environment: A Cavium and Cadence Case Study - Cadence Design Systems Industrial IoT Case Study
Accelerating Timing Closure on High-Speed Interfaces with Allegro TimingVision Environment: A Cavium and Cadence Case Study
Cavium, a company that develops highly integrated semiconductor processors, was facing a significant challenge in their PCB design process. The manual process of board routing was time-consuming, especially as chips increasingly used standards-based high-speed interfaces, had increasingly sensitive signals, and had more complex electrical and layout implementation constraints. The company's Post-Silicon Validation team, responsible for designing evaluation boards to confirm the correct operation and electrical characteristics of the company’s network processors, was spending 8 to 12 weeks on routing critical high-speed signals by hand. This was without using additional human resources. As the volume of chips requiring evaluation boards grew, schedule pressures were increasing. The team needed to have their boards ready when the chip came back from the fab, and as the number of network processors offered by Cavium increased, so did the number of designs.
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Accelerating Network Switch Design: A Case Study of QLogic and Cadence - Cadence Design Systems Industrial IoT Case Study
Accelerating Network Switch Design: A Case Study of QLogic and Cadence
QLogic, a leader in converged networking, enterprise Ethernet, and storage area networking (SAN) products, was faced with the challenge of quickly producing a sophisticated new network switch to capture market share. The company needed to consistently deliver technologies that transform data centers and storage networks globally. The challenge was to speed up the design and verification of a complex new network switch, a multi-million-gate system on chip (SoC), to drive scalable, non-blocking switch architectures across various protocols required from data center-class switching solutions. The complexity of the new design and the need to simulate the full ASIC before tapeout added to the challenge.
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Spansion and Cadence: A Case Study on Improving Designer Productivity and Time to Market - Cadence Design Systems Industrial IoT Case Study
Spansion and Cadence: A Case Study on Improving Designer Productivity and Time to Market
Spansion, a leading provider of Flash memory technology, faced significant challenges in improving designer productivity and compressing time to market. The company's electronic design automation (EDA) tools were no longer sufficient, and a more automated, industry-standard solution was needed. The company also sought to incorporate a more automated approach to custom layout and adopt a front-to-back analog/mixed-signal design flow. The process design kit (PDK), a complete set of technology files enabling analog/mixed-signal custom IC circuit design, was a critical component of this design flow. However, the development and testing of PDKs were time-consuming and costly.
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Xilinx and Cadence: Enhancing IP Design Testing Through IoT - Cadence Design Systems Industrial IoT Case Study
Xilinx and Cadence: Enhancing IP Design Testing Through IoT
Xilinx, a leading FPGA provider, offers a variety of soft and hard IP cores to its customers. These IP cores represent hundreds of communication standards, memory interfaces, DSP functions, floating point operators, interconnects, and CPUs. However, the company faced a significant challenge in testing its IP designs with all relevant combinations of parameter values. This exhaustive process required testing all major design modes with all possible data-width values. The conventional solution of creating an exhaustive permutation set of all parameters was not feasible due to the high number of combinations and the long turnaround time for running a regression. Xilinx needed a solution that could randomly generate parameter sets, considering the legal values of all parameters and the dependencies between them, while avoiding parameter set repetition and redundant duplication of test suite regressions.
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RivieraWaves' Successful Migration to UVM for Enhanced Bluetooth 4.1 IP Design Verification - Cadence Design Systems Industrial IoT Case Study
RivieraWaves' Successful Migration to UVM for Enhanced Bluetooth 4.1 IP Design Verification
RivieraWaves, a startup specializing in wireless connectivity semiconductor intellectual property (IP), faced a significant challenge in producing highly differentiated low-power Bluetooth 4.1 IP within aggressive timeframes. The company had been using Open Verification Methodology (OVM) for its Bluetooth 4.0 designs. However, due to a competitive need to increase automation and produce low-power products in shorter time-to-market windows, RivieraWaves decided to migrate to Universal Verification Methodology (UVM) for its next-generation Bluetooth 4.1 IP designs. The company needed a verification environment and solution that would keep pace with this migration and enable faster IP verification and integration into Bluetooth devices than previously possible. The challenge also included finding bugs faster and sooner, effectively managing new, complex IP challenges, and meeting robustness goals while achieving new levels of efficiency.
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Accelerating Mobile Computing Chip Development: A Case Study of Nufront and Cadence - Cadence Design Systems Industrial IoT Case Study
Accelerating Mobile Computing Chip Development: A Case Study of Nufront and Cadence
Nufront, a Chinese technology company, was tasked with the challenge of developing its third-generation mobile computing chip, the NS115, based on the ARM® Cortex™-A9 dual-core processor. The company had to adhere to strict mobile-computing platform requirements, achieve extremely low levels of power consumption, and ensure a high level of performance. The design team’s challenge was to verify and emulate the chip with a focus on performance and power with Android applications. The NS115 required a complex design with 12 million (12M) gates and had to meet Android system requirements, including the need for external storage, multiple screen displays, the ability to accept data input from various sources, and a long lead-time for IC simulation. The Nufront team felt that register-transfer level (RTL) simulation would be too slow for system-level verification, and frequent design iterations and the lack of full debug visibility wasn’t suitable to choose a field-programmable gate array (FPGA)-based solution.
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Streamlining Library Management and Boosting Productivity: Tait Communications and Cadence - Cadence Design Systems Industrial IoT Case Study
Streamlining Library Management and Boosting Productivity: Tait Communications and Cadence
Tait Communications, a New Zealand-based company that designs and manages digital wireless communications environments, was facing significant challenges in managing schematic and footprint library models. The process was manual, involving spreadsheets and custom-written scripts and utilities, which was both time-consuming and labor-intensive. The company often duplicated efforts due to difficulties in locating specific parts among the thousands they manage. The manual methodology was also prone to errors, leading to inconsistent and inaccurate results. Additionally, Tait needed a solution that could manage design reuse modules, as their PCB designs were unique and subject to various rigid requirements and regulations. They needed version control and the ability to guarantee the accuracy of the components on their boards.
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Newport Media's Enhanced Verification Process with Cadence Solutions - Cadence Design Systems Industrial IoT Case Study
Newport Media's Enhanced Verification Process with Cadence Solutions
Newport Media, a fabless semiconductor company, was faced with the challenge of delivering highly integrated receiver solutions with unprecedented performance, power consumption, size, and cost-efficiency. The company's development team was tasked with developing the verification environment for a new version of the design featuring an external bus interface. The block under verification featured 40K logic gates, including an AHB master/slave interface, an external microprocessor interface, and a direct memory access (DMA) engine. The team needed to expose hard-to-find bugs early in the design cycle of AHB master/slave to verify protocol compliance and write more extensive tests to uncover and explore corner cases.
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NetSpeed Systems Utilizes Cadence Solutions for Efficient Verification of Complex IP Products - Cadence Design Systems Industrial IoT Case Study
NetSpeed Systems Utilizes Cadence Solutions for Efficient Verification of Complex IP Products
NetSpeed Systems, a provider of scalable, coherent, on-chip network (NoC) IPs to system-on-chip (SoC) designers, faced significant challenges in designing its cache-coherent NoC solution, Gemini. The product's flexibility allowed for an endless number of configurations, necessitating an astronomical number of test cases. This posed a risk of introducing prolonged delays in the development schedule. Additionally, the coherency verification process was deeply stateful, requiring long runs to accumulate internal chip states and hit corner cases. Coherency bugs were unforgiving, with a single bug capable of bringing down the entire product. The vast verification space, including a large warm-up period and the need to expose bugs that manifest only after millions of cycles, added to the complexity. The company needed a solution that could provide comprehensive test coverage in this massive verification space, generate all possible NoC configurations, provide an intelligent, coordinated stimulus for the test cases, and enable efficient debugging and reproduction of errors.
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Uniquify's Success with Cadence for Enhanced SoC Design and Manufacturing - Cadence Design Systems Industrial IoT Case Study
Uniquify's Success with Cadence for Enhanced SoC Design and Manufacturing
Uniquify, a leading provider of system-on-chip (SoC) design, manufacturing, and intellectual property solutions, faced the challenge of maintaining its high customer satisfaction levels and reputation by achieving 100% tapeout success. The company had set a high bar for itself in multiple application domains, including image processing, networking, digital television, DSL, mobile phones, digital cameras and displays, multimedia processing, and audio processing. To meet today’s aggressive performance, power, and cost goals, Uniquify engineers had to perform comprehensive physical design space exploration and feasibility analysis early in the design process. Given the complexity and size of today’s designs, they needed systems with the capacity to handle 100M instances and more.
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Faraday's Transformation with Cadence's Encounter Conformal ECO Designer - Cadence Design Systems Industrial IoT Case Study
Faraday's Transformation with Cadence's Encounter Conformal ECO Designer
Faraday Technology Corporation, a leading fabless ASIC vendor and SIP provider, faced a significant challenge in updating its engineering change order (ECO) process. The ECO process involves inserting a logic change directly into the netlist after an automatic tool has already processed it. This could include anything from adding or removing logic in a design to a more subtle change such as cleaning up routing for signal integrity. However, ECOs can be stressful and time-consuming. Traditional manual ECO flows are labor-intensive and limited in their ability to ensure that a product will function properly. Designers often don't know if a change made in the logical netlist can be executed in the physical netlist, making the manual ECO process time-consuming and effort-intensive. It was also difficult to accurately keep track of used spare cells and freed cells.
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Fuji Electric's Accelerated Power IC Design with Cadence Solutions - Cadence Design Systems Industrial IoT Case Study
Fuji Electric's Accelerated Power IC Design with Cadence Solutions
Fuji Electric (FE), a global company based in Japan, was faced with the challenge of developing a new driver IC for its power modules and power ICs. The company needed a control function that could meet the specifications of a new power-management system. The design team had to explore a new control algorithm, including the design concept for the new power-management system. The IC would need to support many functions, such as a protection function to stop the system in case of unusual conditions, such as high or low voltage during a lightning storm. The aggressive time-to-market requirements for this new low-power, low-noise, low-cost power-supply IC added to the complexity of the task. The team also needed to increase the efficiency of the concept design and manage complex verification items.
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Altair's Success in LTE Market with Cadence's Analog IP Solutions - Cadence Design Systems Industrial IoT Case Study
Altair's Success in LTE Market with Cadence's Analog IP Solutions
Altair, a fabless chip company specializing in high-performance, low-power 4G Long-Term Evolution (LTE) semiconductor solutions, faced several challenges in its quest to capture market share in the rapidly growing LTE market. The advanced LTE technologies required high levels of signal processing and careful design to minimize power consumption and maximize performance. The company also had to deal with high costs related to intellectual property (IP) licensing of different system-on-a-chip (SoC) components, tapeouts in advanced process geometries, carrier certifications, and significant software investments. Furthermore, Altair had to meet aggressive time-to-market and price targets for its chipsets. The company's product portfolio, divided into Supercharged LTE and LTE for IoT, presented different challenges, whether it was to enhance performance or reduce power consumption.
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UPEK and Cadence: Enhancing Design Efficiency with Assertion-Based Verification Methodology - Cadence Design Systems Industrial IoT Case Study
UPEK and Cadence: Enhancing Design Efficiency with Assertion-Based Verification Methodology
UPEK, a California-based pioneer in biometric fingerprint technology, faced a significant challenge in its design and verification process. The company's design team was responsible for both design and verification elements of the flow, necessitating a high degree of flexibility to accommodate multiple interfaces across diverse computing systems. The primary business challenge was to provide customers with a faster time to market. To achieve this, UPEK needed to speed up the design cycle and incorporate an assertion-based verification methodology into its existing design and verification flow.
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