Cadence Design Systems > Case Studies > Freescale Semiconductor's Transition to UVM-MS for Enhanced Verification Efficiency

Freescale Semiconductor's Transition to UVM-MS for Enhanced Verification Efficiency

Technology Category

Analytics & Modeling - Digital Twin / Simulation
Sensors - Temperature Sensors

Applicable Industries

Automotive
Semiconductors

Applicable Functions

Product Research & Development
Quality Assurance

Use Cases

Manufacturing Process Simulation
Virtual Reality

Services

System Integration
Testing & Certification

About The Customer

Freescale Semiconductor, Inc. is a leading provider of embedded processing solutions for various markets including automotive, consumer, industrial, and networking. The company's technologies encompass microcontrollers, microprocessors, sensors, and analog ICs. With its headquarters in Austin, Texas, Freescale Semiconductor has design, research and development, manufacturing, and sales operations in over 20 countries. The company's analog and sensors division primarily manages analog components, despite the rapidly increasing use of digital logic in every new project. The division's analog engineers, who have limited expertise in design verification languages, play a critical role in executing top-level verification of mixed-signal systems on chip (SoCs).

The Challenge

Freescale Semiconductor, a leader in embedded processing solutions, faced a significant challenge in improving the efficiency of top-level verification of mixed-signal Systems on Chip (SoCs). The company's analog and sensors division, which primarily manages analog components, was grappling with the increasing use of digital logic in new projects. Most analog engineers had limited expertise in design verification languages, yet their involvement in executing top-level verification of mixed-signal SoCs was crucial. The traditional testbenches created by analog engineers were based on schematic entry and multiple configuration views, and relied on waveform inspection. However, advanced verification methodologies were typically digital-centric, command-line driven, and based on object-oriented languages such as SystemVerilog. This posed a significant challenge in bridging the gap between analog and digital verification methodologies.

The Solution

To address this challenge, Freescale Semiconductor's verification team developed a digital-centric verification environment using a domain-specific language based on pre-processor macros and SystemVerilog APIs. This environment allowed analog engineers to perform self-checking top-level simulations. With Verilog configurations, users could select the design under test (DUT) abstraction required for each test case. The team then integrated the Universal Verification Methodology (UVM) into the design verification environment of their next-generation battery-monitoring IC. Freescale Semiconductor used Cadence® Virtuoso® Analog Design Environment to implement its UVM/mixed-signal methodology. The team also utilized the new unified netlister technology in Virtuoso Analog Design Environment, which accelerated the process of netlisting and elaborating a simulator snapshot with Cadence Virtuoso AMS Designer Simulator. They used the Cadence SimVision Debug environment in Cadence Incisive® Enterprise Simulator to debug their mixed-signal designs and the Cadence Incisive vManager™ solution for better coverage and traceability.

Operational Impact

The transition to UVM and the implementation of a digital-centric verification environment resulted in a significant improvement in Freescale Semiconductor's verification process. The new methodology was quickly adopted by the company's analog designers, who could continue to develop directed tests using mixed-signal configurations in SPICE/behavior Verilog-AMS abstraction. Design verification engineers could complement top-level verification with UVM-powered constrained random stimulus using wreal configurations. The new methodology not only fostered 2X better productivity at the top level for both analog and digital verification engineers but also significantly reduced the verification effort for derivative products. The company achieved better coverage and improved detection of hard-to-find bugs, enhancing the overall quality and reliability of their products.

Quantitative Benefit

Significantly faster top-level verification of mixed-signal SoCs using wreal configurations
2X more verification productivity for digital and analog engineers achieved through rapid simulation launch and re-invoke
Improved coverage and traceability with Incisive vManager solution