Cadence Design Systems > Case Studies > Xilinx and Cadence: Enhancing IP Design Testing Through IoT

Xilinx and Cadence: Enhancing IP Design Testing Through IoT

Technology Category

Analytics & Modeling - Digital Twin / Simulation
Functional Applications - Enterprise Resource Planning Systems (ERP)

Applicable Industries

Semiconductors

Applicable Functions

Product Research & Development
Quality Assurance

Use Cases

Digital Twin
Virtual Reality

Services

Testing & Certification

About The Customer

Xilinx is a leading provider of Field Programmable Gate Arrays (FPGAs). The company offers a variety of soft IP cores for customers to build into their designs, as well as hard IP blocks implemented in silicon during fabrication. These offerings accelerate the development process through IP use and reuse. Xilinx's rich set of IP cores represents hundreds of communications standards, memory interfaces, DSP functions, floating point operators, interconnects, and even CPUs. To facilitate customer design customization for specific end applications, Xilinx IP solutions provide many user-configurable attributes.

The Challenge

Xilinx, a leading FPGA provider, offers a variety of soft and hard IP cores to its customers. These IP cores represent hundreds of communication standards, memory interfaces, DSP functions, floating point operators, interconnects, and CPUs. However, the company faced a significant challenge in testing its IP designs with all relevant combinations of parameter values. This exhaustive process required testing all major design modes with all possible data-width values. The conventional solution of creating an exhaustive permutation set of all parameters was not feasible due to the high number of combinations and the long turnaround time for running a regression. Xilinx needed a solution that could randomly generate parameter sets, considering the legal values of all parameters and the dependencies between them, while avoiding parameter set repetition and redundant duplication of test suite regressions.

The Solution

To address this challenge, Xilinx incorporated the Cadence Incisive Enterprise Simulator with Specman macros for enhanced parameter generation. This pre-simulation step became part of their regression flow. Cadence provided a macro for specifying which parameter sets needed to be exhaustively generated and which fields could be simply randomized, with as little repetition as possible. The solution was built on top of the Specman e language. This solution offered several advantages including flexibility, ease of use, and runtime improvements. It enabled easy layering of constraints, explicit generation of exhaustive sets, and random generation of other parameters without repetition. The solution was easy to use, requiring the end user to only specify the parameter values and constraints. The runtime improvements were significant, with the process that used to take over an hour now being manageable and efficient.

Operational Impact

The implementation of the Cadence Incisive Enterprise Simulator with Specman technology has resulted in significant operational improvements for Xilinx. The solution has increased productivity for both hard and soft IP development and improved overall IP quality. Several cores have already been using the attribute generation solution in their regression successfully. Xilinx has recently released an internal regression management tool which uses this solution, and plans to deploy it on all silicon IP teams. The solution has also simplified the process for end users, requiring them to only specify the parameter values and constraints. This has made the solution easy to use and intuitive overall.

Quantitative Benefit